Example embodiments relate to non-volatile memory devices and to methods of manufacturing the same, and more particularly, to flash memory devices and methods of manufacturing flash memory devices.
Semiconductor memory devices may generally be classified as either volatile or non-volatile memory devices. Volatile memory devices (e.g., dynamic random access memory devices and static random access memory devices) may have relatively higher input/output (I/O) speeds, but lose data stored therein when power to the device is shut off. Non-volatile memory devices (e.g., read-only memory devices and electrically erasable programmable read-only memory devices) maintain data stored therein even when power is shut off. Flash memory devices are an advanced type of electrically erasable programmable read-only memory which can erase data at relatively high speeds.
In a flash memory device, a plurality of stacked gate structures are arranged in a cell region of a semiconductor substrate. The semiconductor substrate may comprise a bulk semiconductor substrate or a semiconductor layer that is formed on a semiconductor or non-semiconductor substrate. Each stacked gate structure includes a tunnel oxide pattern (e.g., a gate oxide pattern), a floating gate pattern and a control gate pattern. The floating gate pattern and the control gate pattern are separated by a dielectric layer.
In response to electric voltages that are applied to the substrate and the floating gate pattern, electrons may be either pushed into or pulled out of the floating gate pattern via a Fowler-Nordheim (F-N) tunneling mechanism and/or a channel hot electron injection mechanism in order to store or erase data. The voltage may be applied to the floating gate pattern through the dielectric layer.
A tunnel oxide layer is formed in the cell region of the substrate. The floating gate pattern, the dielectric layer and the control gate pattern are then stacked on the tunnel oxide layer, thereby forming the stacked gate structure in the cell region of the substrate.
A high coupling ratio is required between the floating gate pattern and the control gate pattern in order to induce the voltage applied to the control gate pattern to the floating gate pattern. The coupling ratio is a function of both the surface area and the thickness of the dielectric layer, with larger surface areas and smaller thicknesses both acting to increase the coupling ratio. However, if the thickness of the dielectric layer is reduced too much, the electrons in the dielectric layer may tend to leak into the floating gate pattern, thereby deteriorating the charge retention characteristics of the floating gate pattern. Consequently, the surface of the dielectric layer tends to be enlarged as necessary to increase the coupling ratio.
Since the floating gate pattern typically is formed using doped polysilicon, it may be difficult to form the dielectric layer as a thin thermal oxide layer on the floating gate pattern. In addition, there is a problem that the thin thermal oxide layer may exhibit excessive leakage currents. Consequently, a multilayer structure that includes a sequentially stacked first oxide layer, followed by a nitride layer, followed by a second oxide layer is usually used as the dielectric layer in a flash memory device. Such an oxide/nitride/oxide dielectric layer (hereinafter, referred to as ONO layer) has a dielectric constant that is larger than the dielectric constant of a thermal oxide layer.
In a conventional flash memory device, the floating gate pattern comprises a plurality of floating gates that are formed on line-shaped active regions. A device isolation layer is formed on a field region portion of the substrate, and this field region (and/or the device isolation layer thereon) may define the active region portion of the substrate. An upper surface of the device isolation layer may be lower than an upper surface of the floating gate pattern. Thus, a field recess is provided between neighboring floating gates and side surfaces of the floating gates are exposed to the field recess. The dielectric layer is formed on the device isolation layer and the floating gate pattern along a surface profile of the substrate including the field recess. Thus, the side surfaces and a top surface of the floating gate pattern are covered with the dielectric layer. Therefore, the width of the field recess is reduced by the thickness of the dielectric layer on the sidewalls of the adjacent floating gate lines. A polysilicon layer is formed on the dielectric layer to fill the field recess, to thereby form the control gate pattern of the flash memory device.
Unfortunately, the reduction in the width of the field recess that results from forming the dielectric layer on the side surfaces of the floating gates may cause non-uniform deposition of the polysilicon layer, and thus various process defects such as voids and/or seams may be formed in the control gate pattern. Moreover, as the integration density of flash memory devices is increased, the gap distance between the floating gates is reduced, and hence an aspect ratio of the field recess tends to be increased. With such higher aspect ratios, the likelihood that voids and/or seams may be generated is increased.
The presence of voids and/or seams in the control gate pattern may reduce the coupling ratio of the flash memory device, which may deteriorate the electric characteristics of the flash memory device. Particularly, when a heat treatment is conducted on the polysilicon layer for purposes of reducing the specific resistance of the control gate pattern, the silicon bonds (Si—Si bond) are frequently broken, and silicon (Si) atoms may migrate to the boundary surface between the dielectric layer and the control gate pattern. Thus, a depletion field is intensively found between the dielectric layer and the control gate pattern due to the heat treatment.